DEEP-SUBMICROMETER LARGE-ANGLE-TILT IMPLANTED DRAIN (LATID) TECHNOLOGY

A deep-submicrometer large-angle-tilt implanted drain (LATID) technology is comprehensively described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. As a result of investigating over a wide range of process conditions through experiments and device simulation, a design guideline that offsets the n+ implant by sidewall spacers to suppress the n+-gate overlap to zero while keeping the n- region fully overlapped with the gate is found to be crucial for improved performance and reliability. More offsetting of the n+ implant than this leads to reduced current drive I(D) due to the nonoverlapped n- region like the LDD case, while less off setting leads to degraded hot-carrier lifetime tau(life) due to the insufficient n- length L(n-) for reducing electric field. Especially for a LATID without spacers, a sufficient L(n-) cannot be obtained without making the gate-drain overlap length L(ov) as large as >0.15-mu-m. On the other hand, an optimum 1/4-mu-m LATID device with spacer length of 0.08-mu-m achieves approximately 30% improved I(D), approximately 15% improved circuit speed due to comparably small overlap capacitance, and approximately 2000 times improved tau(life) of 10(3) years as compared with LDD together with suppressed L(ov) of approximately 0.09-mu-m and short-channel effects, all under 3.3-V operation. The LATID technology, with spacers, is most promising for 3.3-V operation of deep-submicrometer ULSI's.