A BICMOS PROGRAMMABLE FREQUENCY-DIVIDER

被引：3

作者：

CHOY, CS ^{[1
]}

HO, CY ^{[1
]}

LUNN, G ^{[1
]}

LIN, B ^{[1
]}

FUNG, G ^{[1
]}

机构：

[1] MOTOROLA SEMICOND HONG KONG LTD,BIOPOLAR IC DESIGN,TAI PO,HONG KONG

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1992年 / 39卷 / 03期

关键词：

Computer Simulation - Integrated Circuits; VLSI - Layout - Logic Circuits; Emitter Coupled - Phase Locked Loops;

D O I：

10.1109/82.127298

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a BiCMOS programmable frequency divider, which is a major functional block of a frequency synthesis IC based on a phase-locked loop. Innovative techniques are demonstrated to solve many incompatibility problems between ECL and CMOS techniques. It shows that a similar concept can be applied to other high-speed designs. The frequency divider has 15 stages and operates at 165 MHz. It occupies 0.375 mm2 of die area, which is only a third of what is required in a all bipolar version. Power consumption is about 55 mW, which is 80% of that of the all-bipolar version.

引用

页码：147 / 154

页数：8