A 3.5-NS, 2-W, 20-MM2, 16-KBIT ECL BIPOLAR RAM

被引:9
作者
HOMMA, N [1 ]
YAMAGUCHI, K [1 ]
NANBU, H [1 ]
KANETANI, K [1 ]
NISHIOKA, Y [1 ]
UCHIDA, A [1 ]
OGIUE, K [1 ]
机构
[1] HITACHI LTD,CTR DEVICE DEV,OHME,TOKYO 198,JAPAN
关键词
D O I
10.1109/JSSC.1986.1052594
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:675 / 680
页数:6
相关论文
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[4]   A 4.5 NS ACCESS TIME 1KX4 BIT ECL RAM [J].
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IKUSHIMA, T ;
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MAYUMI, H ;
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NAKAMURA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :515-520
[5]  
TOKUYOSHI F, 1984, FEB ISSCC, P220
[6]  
YAMAGUCHI K, 1984, SEP VLSI, P52