SUGGESTION FOR AN IC FAST PARALLEL MULTIPLIER

被引：30

作者：

DEMORI, R

机构：

[1] Instituto Elettrotecnico Nazionale Galileo Ferraris, Torino

来源：

ELECTRONICS LETTERS | 1969年 / 5卷 / 03期

关键词：

D O I：

10.1049/el:19690034

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A general method for handling partial products in a parallel multiplier is proposed. It leads to a network of and gates and full adders, availables as I.C.S. which can have an operation time of less than 10 ns per bit of the result. © 1969, The Institution of Electrical Engineers. All rights reserved.

引用

页码：50 / &