RECIRCULATING ULTRASONIC STORES - AN ECONOMICAL APPROACH TO SEQUENTIAL STORAGE WITH BIT RATES BEYOND 100 MHZ

State of the art integrated circuits and ultrasonic delay lines can be combined to form batch‐fabricated digital storage modules having random access to sequentially stored blocks of information. Greatest economy is indicated if such stores are designed for as high a bit rate as is technologically feasible, at present limited by the speed of available integrated circuitry. A store of optimum design will have a block size of approximately 1000 bits which, for a bit rate of 100 MHz, gives a maximum latency time of approximately 10 microseconds. Such designs are realizable with zero temperature coefficient material. The stores can be used as main memories for small computers or as fast transfer stores shuttling information between a slow external bulk memory and a very fast random access memory in large computers. A variety of accessing modes permit these stores to operate over a large range of access rates without requiring large buffer stores. © 1969 The Bell System Technical Journal