A 1-MBIT BICMOS DRAM USING TEMPERATURE-COMPENSATION CIRCUIT TECHNIQUES

被引：11

作者：

KITSUKAWA, G

ITOH, K

HORI, R

KAWAJIRI, Y

WATANABE, T

KAWAHARA, T

MATSUMOTO, T

KOBAYASHI, Y

机构：

[1] HITACHI LTD,MUSASHI WORKS,KODAIRA,TOKYO,JAPAN

[2] HITACHI LTD,CTR DEVICE DEV,OHME,TOKYO,JAPAN

[3] HITACHI LTD,HITACHI RES LAB,HITACHI,IBARAKI 316,JAPAN

来源：

关键词：

D O I：

10.1109/4.32013

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：597 / 602

页数：6

共 11 条

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[2] EIDLAR RJ, 1970, ISSCC FEB, P158
[3] FURUYAMA T, 1986, ISSCC, P272
[4] Higuchi H., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P694
[5] Iijima H., 1986, Hitachi Review, V35, P255
[6] ITOH K, 1984, ISSCC, P282
[7] AN EXPERIMENTAL 1-MBIT BICMOS DRAM
KITSUKAWA, G
HORI, R
KAWAJIRI, Y
WATANABE, T
KAWAHARA, T
ITOH, K
KOBAYASHI, Y
OOHAYASHI, M
ASAYAMA, K
IKEDA, T
KAWAMOTO, H
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) : 657 - 662
[8] Kobayashi Y., 1986, International Electron Devices Meeting 1986. Technical Digest (Cat. No.86CH2381-2), P802
[9] MANO T, 1983, IEEE ISSCC, P234
[10] 13-NS, 500-MW, 64-KBIT ECL RAM USING HI-BICMOS TECHNOLOGY
OGIUE, K
ODAKA, M
MIYAOKA, S
MASUDA, I
IKEDA, T
TONOMURA, K
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) : 681 - 685