LOW-POWER CHIP INTERCONNECTION BY DYNAMIC TERMINATION

被引：5

作者：

KAWAHARA, T ^{[1
]}

HORIGUCHI, M ^{[1
]}

ETOH, J ^{[1
]}

SEKIGUCHI, T ^{[1
]}

KIMURA, K ^{[1
]}

AOKI, M ^{[1
]}

机构：

[1] HITACHI LTD,DIV SEMICOND & INTEGRATED CIRCUITS,KODAIRA,TOKYO 187,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1995年 / 30卷 / 09期

关键词：

D O I：

10.1109/4.406404

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power dynamic termination scheme is: proposed and demonstrated as a way to reduce power dissipation for high-speed data transport. In this scheme, the transmission lines are terminated only if the signals change. The gate of a switching MOS transistor connected to a termination resistor is driven by differentiating the transmission signal with a resistor and a capacitor. The power dissipation of the terminating resistor can be reduced to 1/5 in the conventional de termination scheme, and overshoot can be reduced to 1/5 that in the open scheme. This scheme is promising for use with palm-top equipment, facilitating high-speed low power operation.

引用

页码：1030 / 1034

页数：5