FORMAL METHODOLOGY FOR FAULT TREE CONSTRUCTION

被引:41
作者
FUSSELL, JB [1 ]
机构
[1] GEORGIA INST TECHNOL,ATLANTA,GA 30332
关键词
ELECTRIC NETWORKS - Computer Aided Analysis;
D O I
10.13182/NSE73-A23308
中图分类号
TL [原子能技术]; O571 [原子核物理学];
学科分类号
0827 ; 082701 ;
摘要
A model is presented for formulating the Boolean failure logic, called the fault tree, for electrical systems from associated schematic diagrams and system-independent component information. The model is developed in detail for electrical systems, while its implication and terminology extend to all fault tree construction. This method offers the opportunity for both qualitative and quantitative analysis. The methodology was verified by a computer.
引用
收藏
页码:421 / 432
页数:12
相关论文
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