VERSATILE MULTIPLIER ARRAYS

被引:5
作者
DEAN, KJ
机构
[1] Department of Science & Electrical Engineering, College of Technology, Letchworth, Herts
关键词
D O I
10.1049/el:19680260
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Recent letters have described two multiplier arrays. It is now proposed that these arrays are more versatile than was formerly supposed. They can be used both as multipliers and as adders, either separetely or together, giving a parallel binary output. © 1968, The Institution of Electrical Engineers. All rights reserved.
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收藏
页码:333 / &
相关论文
共 2 条
[1]   HIGH-SPEED ITERATIVE MULTIPLIER [J].
BURTON, DP ;
NOAKS, DR .
ELECTRONICS LETTERS, 1968, 4 (13) :262-&
[2]   ITERATIVE LOGICAL NETWORK FOR PARALLEL MULTIPLICATION [J].
HOFFMANN, JC ;
LACAZE, B ;
CSILLAG, P .
ELECTRONICS LETTERS, 1968, 4 (09) :178-&