ULTRAFAST OPERATION OF 5TH-ADJUSTED P(+)-N(+) DOUBLE-GATE SOI MOSFETS

To optimize the V-th of double-gate SOI MOSFET's, we fabricated devices with p(+) poly-Si for the front-gate electrode and n(+) poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V-th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 mu m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects.