A CMOS 4-CHANNEL X 1K TIME MEMORY LSI WITH 1-NS/B RESOLUTION

被引：37

作者：

ARAI, Y ^{[1
]}

MATSUMURA, T ^{[1
]}

ENDO, K ^{[1
]}

机构：

[1] NIPPON TELEGRAPH & TEL PUBL CORP, LSI LABS, ATSUGI, KANAGAWA 24301, JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 03期

关键词：

D O I：

10.1109/4.121558

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A four-channel 1024-b time-to-digital converter chip, which records input signals to memory cells at 1-ns intervals, has been developed. To achieve 1-ns precision, the chip incorporates a feedback stabilized delay element. The chip was fabricated on a 5.0-mm x 5.6-mm die using 0.8-mu-m CMOS technology. It dissipates only 7 mW/channel under typical operating conditions.

引用

页码：359 / 364

页数：6

共 3 条

[1]

Arai Y., 1988, 1988 Symposium on VLSI Circuits: Digest of Technical Papers (IEEE Cat. No.88TH0227-9), P121

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