A 3RD-ORDER MULTISTAGE SIGMA-DELTA MODULATOR WITH REDUCED SENSITIVITY TO NONIDEALITIES

被引：26

作者：

RIBNER, DB ^{[1
]}

BAERTSCH, RD ^{[1
]}

GARVERICK, SL ^{[1
]}

MCGRATH, DT ^{[1
]}

KRISCIUNAS, JE ^{[1
]}

FUJII, T ^{[1
]}

机构：

[1] SEIKO INSTRUMENTS USA INC,SUNTO,SHIZUOKA 41013,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 12期

关键词：

D O I：

10.1109/4.104167

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multistage third-order sigma-delta modulator, which is unconditionally stable and has a low sensitivity to component mismatch and op-amp performance limitations, has been designed and fabricated in a 1.2-mu-m CMOS double-poly technology. The modulator, consisting of cascaded second- and first-order stages, is scaled to prevent performance degradation from integrator overload. In addition, the first-stage integrator output is used directly, instead of its quantization error, to facilitate ratioless input circuitry in the second stage. Experimental results indicate a signal-to-noise ratio (S/N) of 93 and 90 dB at a signal-to-distortion ratio (S/D) of 93 dB for sample rates of 24 and 80 kHz, respectively.

引用

页码：1764 / 1774

页数：11

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