Parallel Resonant DC Link Circuit-A Novel Zero Switching Loss Topology with Minimum Voltage Stresses

被引:44
作者
He, Jin [1 ]
Mohan, Ned [1 ]
机构
[1] Univ Minnesota, Dept Elect Engn, 4-174 EE-C Sci Bldg,200 Union St SE, Minneapolis, MN 55455 USA
关键词
Electric Inverters - Electric Losses - Electric Networks--Topology - Pulse Width Modulation;
D O I
10.1109/63.97769
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A parallel-resonant dc link (PRDCL) circuit topology as new approach to realizing zero switching loss dc-ac high switching frequency power conversion is presented. The proposal circuit is used as an interface between dc voltage supply and the voltage source PWM inverter to provide a short zero voltage period in the dc link of the inverter to allow zero voltage switchings to take place in the PWM inverter. Moreover, the peak voltage stress on the PWM inverter switches is limited to the dc supply voltage V-s. Another significant advantage of the proposed circuit is that the inverter can be controlled by the conventional PWM strategy. The proposed circuit has been systematically analyzed and its operation principle has been explained in detail. Design considerations and design formulas are also presented. A complete zero voltage switching dc-ac system consisting of the proposed circuit and the PWM inverter is simulated on computer.
引用
收藏
页码:687 / 694
页数:8
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