SYNTHESIS OF MULTIPLE-INPUT CHANGE ASYNCHRONOUS MACHINES USING CONTROLLED EXCITATION AND FLIP-FLOPS

被引:14
作者
CHUANG, HYH [1 ]
DAS, S [1 ]
机构
[1] WASHINGTON UNIV, COMP SYST LAB, ST LOUIS, MO 63110 USA
关键词
D O I
10.1109/T-C.1973.223656
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:1103 / 1109
页数:7
相关论文
共 21 条
[1]   GENERATION OF A CLOCK PULSE FOR ASYNCHRONOUS SEQUENTIAL MACHINES TO ELIMINATE CRITICAL RACES [J].
BREDESON, JG ;
HULINA, PT .
IEEE TRANSACTIONS ON COMPUTERS, 1971, C 20 (02) :225-+
[2]   TRANSITION LOGIC CIRCUITS AND A SYNTHESIS METHOD [J].
CHUANG, YH .
IEEE TRANSACTIONS ON COMPUTERS, 1969, C 18 (02) :154-&
[3]  
CHUANG YH, 1972, 10 P ANN ALL C CIRC, P647
[4]  
EICHELBERGER EB, 1962, 19 PRINC U DIG SYST
[5]   SYNTHESIS OF ASYNCHRONOUS SEQUENTIAL CIRCUITS WITH MULTIPLE-INPUT CHANGES [J].
FRIEDMAN, AD ;
MENON, PR .
IEEE TRANSACTIONS ON COMPUTERS, 1968, C 17 (06) :559-+
[6]   AVOIDANCE AND ELIMINATION OF FUNCTION HAZARDS IN ASYNCHRONOUS SEQUENTIAL CIRCUITS [J].
HACKBART, RR ;
DIETMEYER, DL .
IEEE TRANSACTIONS ON COMPUTERS, 1971, C 20 (02) :184-+
[7]  
HARING DR, 1966, MIT31 RES MON
[8]  
Hartmanis J., 1966, ALGEBRAIC STRUCTURE
[9]  
Huffman D. A., 1954, J FRANKLIN I, V257, P275
[10]  
Huffman DA, 1954, J FRANKLIN I, V257, P161, DOI [DOI 10.1016/0016-0032(54)90574-8, 10.1016/0016-0032(54)90574-8]