3-DIMENSIONAL INTERCONNECT ANALYSIS USING PARTIAL ELEMENT EQUIVALENT-CIRCUITS

The partial element equivalent circuit (PEEC) technique has been applied successfully for many years to model the electrical properties of high-speed interconnect. In the PEEC approach, interconnect is modeled as a passive RLC circuit with partial inductances and capacitances calculated from a quasi-static solution of Maxwell's equations. The PEEC models are useful for three reasons. They can be combined with other circuit models (like transistors) into an input circuit for a circuit simulator like SPICE or ASTAP. They work equally well in the time and frequency domains and it is easy to model some interconnect in great detail and some crudely. In this paper we extend the PEEC approach to dielectrics and we include retardation (the effect of the finite speed of light). We show that the new retarded partial element equivalent circuit (rPEEC) technique is equivalent to a full-wave solution while keeping the above mentioned advantages of the PEEC approach. In a simple PC-board example we demonstrate noticeable errors when retardation is neglected. We compare rPEEC results with measurements, analytical calculations, and a full-wave solver, and show good agreement.