A +/-5-V CMOS ANALOG MULTIPLIER

被引：74

作者：

QIN, SC

GEIGER, RL

机构：

[1] Texas A&M Univ, College Station,, TX, USA, Texas A&M Univ, College Station, TX, USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 06期

关键词：

COMPUTERS - Multiplying Circuits - INTEGRATED CIRCUITS; VLSI - SEMICONDUCTOR DEVICES; MOS; -; Fabrication;

D O I：

10.1109/JSSC.1987.1052866

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A four-quadrant CMOS analog multiplier is presented. The device is nominally biased with plus or minus 5-V supplies, has identical full-scale single-ended x and y inputs of plus or minus 4 V, and exhibits less than 0. 5% nonlinear error at 75% of full-scale swing. Operation with supplies as low as plus or minus 2. 5 V is also possible. A comparison of theoretical and experimental results obtained from fabrication of the multiplier in a 3- mu m p-well CMOS process is made.

引用

页码：1143 / 1147

页数：5

共 5 条

[1] A 20-V 4-QUADRANT CMOS ANALOG MULTIPLIER [J].