A DIAGONAL ACTIVE-AREA STACKED CAPACITOR DRAM CELL WITH STORAGE CAPACITOR ON BIT LINE

被引：9

作者：

KIMURA, S ^{[1
]}

KAWAMOTO, Y ^{[1
]}

KURE, T ^{[1
]}

HASEGAWA, N ^{[1
]}

KISU, T ^{[1
]}

ETOH, J ^{[1
]}

AOKI, M ^{[1
]}

TAKEDA, E ^{[1
]}

SUNAMI, H ^{[1
]}

ITOH, K ^{[1
]}

机构：

[1] HITACHI VERY LARGE SCALE INTEGRAT ENGN CORP,KODAIRA,TOKYO 187,JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1990年 / 37卷 / 03期

关键词：

D O I：

10.1109/16.47780

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new stacked-capacitor (STC) cell concept for 16-Mbit DRAM's is introduced. The new STC cell features a storage capacitor placed on a bit line and a diagonal active area. This enables a large storage capacitance, 35 fF/bit, to be achieved on a small cell size of 3.36 μm 2. By eliminating completely the structural interferences between bit line and plate electrode, the storage-node pattern is maximized. The new STC cell also features low noise characteristics due to its shielded bit-line structure. This minimizes the interbit-line capacitance to below 1 percent of the bit-line capacitance in the memory array. The average charge retention time, measured using an experimental 2-kbit array, is determined to be 30 s at 40°C. The characteristics of the diagonal active memory cell transistor are comparable to those of a conventional transistor. © 1990 IEEE

引用

页码：737 / 743

页数：7

共 17 条

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