JOSEPHSON LOGIC AND MEMORY CIRCUITS

Josephson logic and memory circuits have rapidly developed over the last few years. Initial exploratory circuits and devices, designed with linewidths of the order of 25µm were soon developed down to linewidths in the 5 to 2.5µm range with perhaps the most significant modification being the change from in-line gates to interferometer devices (SQUIDS) with higher sensitivity, lower capacitance and higher speed. Present devices at a 2.5µm linewidth offer LSI logic chips with typical delays of the order of 30 ps per gate at a total chip dissipation level of 6 mW, including the power supply. NDRO RAM chips with densities of 4K bits/chip are possible for high-speed cache memory with a 2.5µm linewidth technology and an access time of the order of 0.5 ns. For main memory, on the other hand, a 2.5µm minimum linewidth technology is expected to yield approximately 16K bits/chip of DRO RAM with an access time estimated at 15 ns at a dissipation level of only 40 µW/chip. © 1979 IEEE