A PARTIAL SCAN METHOD FOR SEQUENTIAL-CIRCUITS WITH FEEDBACK

This paper presents a method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and for reducing the sequential depth. Tests for the resulting circuit are efficiently generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. We obtained a 98% fault coverage for a 5000 gate circuit by scanning just 5% of the flip-flops. A novel design of scan flip-flop reduces the input pin and signal routing overheads of the added scan clock. © 1990 IEEE