LOW-LATENCY, HIGH-SPEED NUMERICALLY CONTROLLED OSCILLATOR USING PROGRESSION-OF-STATES TECHNIQUE

A progression-of-states design technique for numerically controlled oscillators (NCO's) has measured a decrease in 16-b accumulator latency to two clock cycles for a 130-MHz device in a 1.0-mu-m CMOS gate array. An enhanced version derived and simulated directly from the fabricated device has been projected to accumulate at 267 MHz.