A HIGH-POWER GAAS-FET HAVING BURIED PLATED HEAT SINK FOR HIGH-PERFORMANCE MMICS

This paper reports an FET structure, named ''Advanced SIV FET'' (advanced source island via-hole FET). ''SIV FET'' (source island via-hole FET) [1] is an FET whose every source electrode is grounded to the 40 mu m-thick backside gold PHS metal through via holes for reducing source parasitic inductance, and the substrate thickness is as small as 30 mu m for attaining low thermal resistance. While the developed structure of ''Advanced SIV FET'' contains a selectively formed buried PHS (plated heat sink) instead of having thick backside gold metal. In this FET, the thickness of the substrate under the active layer, which produces heat during operation, is set to be 30 mu m with a buried 70 mu m thick gold plated heat sink for achieving low thermal resistance, and the thickness of other portion of the chip is set to be 100 mu m for low loss in microstrip lines and sufficient mechanical strength. This FET structure has provided higher power output and power added efficiency with great simplicity of wafer and chip handling. The experimental results have shown that an FET, of 1350; gmm gate width, has achieved a superior low thermal resistance of 16 degrees C/W corresponding to a maximum channel temperature of 42.1 degrees C. RF performances, at V-ds = 7 V, shaw a power output as high as 27.9 dBm with a power added efficiency of 32% at the 1 dB power compression point and a linear gain of 8.3 dB all at 18 GHz. It also has achieved an excellent power density of 0.54 W/mm at V-ds = 8 V. This structure has also shown its excellence in mechanical reliability which conforms to MIL-STD-883.