VLSI CHIP INTERCONNECTION TECHNOLOGY USING STACKED SOLDER BUMPS

被引:11
作者
MATSUI, N [1 ]
SASAKI, S [1 ]
OHSAKI, T [1 ]
机构
[1] NIPPON TELEGRAPH & TEL PUBL CORP, MUSASHINO ELECT COMMUN LAB, APPL ELECTR LABS, MUSASHINO, TOKYO 180, JAPAN
来源
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1987年 / 10卷 / 04期
关键词
D O I
10.1109/TCHMT.1987.1134795
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
10
引用
收藏
页码:566 / 570
页数:5
相关论文
共 10 条
[1]   Boundary tension by pendant drops [J].
Andreas, JM ;
Hauser, EA ;
Tucker, WB .
JOURNAL OF PHYSICAL CHEMISTRY, 1938, 42 (08) :1001-1019
[2]  
GOLDMANN LS, 1983, SOLID STATE TECHNOL, V26, P91
[3]   LEAD-INDIUM FOR CONTROLLED-COLLAPSE CHIP JOINING [J].
GOLDMANN, LS ;
HERDZIK, RD ;
KOOPMAN, NG ;
MARCOTTE, VC .
IEEE TRANSACTIONS ON PARTS HYBRIDS AND PACKAGING, 1977, 13 (03) :194-198
[4]   LOW EXPANSIVITY ORGANIC SUBSTRATE FOR FLIP-CHIP BONDING [J].
GREER, SE .
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1979, 2 (01) :140-144
[5]   THERMAL STRESS-FREE PACKAGE FOR FLIP-CHIP DEVICES [J].
KOHARA, M ;
HATTA, M ;
GENJYO, H ;
SHIBATA, H ;
NAKATA, H .
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1984, 7 (04) :411-416
[6]   CONTROLLED COLLAPSE REFLOW CHIP JOINING [J].
MILLER, LF .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1969, 13 (03) :239-&
[7]  
MONES AH, 1984, SOLID STATE TECHNOL, V27, P119
[8]  
PARRIS SR, 1982, VLSI DES, V3, P44
[9]  
SATOH R, 1983, P IEPS, P455
[10]   SLT DEVICE METALLURGY AND ITS MONOLITHIC EXTENSION [J].
TOTTA, PA ;
SOPHER, RP .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1969, 13 (03) :226-&