BEE2: A high-end reconfigurable computing system

被引:111
作者
Chang, Chen [1 ]
Wawrzynek, John [1 ,2 ]
Brodersen, Robert W. [1 ,3 ]
机构
[1] University of California, Berkeley, CA
[2] Berkeley Reconfigurable Architectures, Software, and Systems Group, University of California, Berkeley, CA
[3] Department of Electrical Engineering nad Computer Science, University of California, Berkeley, CA
来源
IEEE Design and Test of Computers | 2005年 / 22卷 / 02期
关键词
Computer systems programming;
D O I
10.1109/MDT.2005.30
中图分类号
学科分类号
摘要
The BEE2 project is developing a reusable, modular, and scalable framework or designing high-end reconfigurable computers, including a processing-module building block and several programming models. Using these elements, BEE2 can provide over 10 times more computing throughput than a DSP-based system with similar power consumption and cost, and over 100 times that of a microprocessor-based system. © 2005 IEEE.
引用
收藏
页码:114 / 125
页数:11
相关论文
共 15 条
[1]  
Chang C., Et al., Implementation of BEE: A Real-Time Large-Scale Hardware Emulation Engine, Proc. 2003 ACM/SIGDA 11th Int'l. Symp. Field-Programmable Gate Arrays, pp. 91-99, (2003)
[2]  
Durbano J.P., Et al., FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method, Proc. 12th Ann. IEEE Symp. Field-Programmable Custom Computing Machines, pp. 156-163, (2004)
[3]  
Chen W., Et al., An FPGA Implementation of the Two-Dimensional Finite-Difference Time-Domain (FDTD) Algorithm, Proc. 2004 ACM/SIGDA 12th Int'l. Symp. Field-Programmable Gate Arrays, pp. 213-222, (2004)
[4]  
DeHon A., Huang R., Wawrzynek J., Hardware-Assisted Fast Routing, Proc. L0th Ann. IEEE Symp. Field-Programmable Custom Computing Machines, (2002)
[5]  
Wrighton M., DeHon A., Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement, Proc. 2003 ACM/SIGDA 11th Int'l. Symp. Field-Programmable Gate Arrays, pp. 33-42, (2003)
[6]  
Callahan T.J., Et al., Fast Module Mapping and Placement for Datapaths in FPGAs, Proc. 1998 ACM/SIGDA 6th Int'l. Symp. Field Programmable Gate Arrays, pp. 123-132, (1998)
[7]  
Xilinx Virtex-4 Data Sheet, (2004)
[8]  
Caliga D., Barker D.P., Delivering Acceleration: The Potential for Increased HPC Application Performance Using Reconfigurable Logic, Proc. SC2001, (2001)
[9]  
Keltcher C.N., Et al., The AMD Opteron Processor for Multiprocessor Servers, IEEE Micro, 23, 2, pp. 66-76, (2003)
[10]  
Xilinx Virtex-II Pro Data Sheet, (2004)