Programmable DSP architectures. - Part 1

被引：30

作者：

Lee, Edward A. ^{[1
]}

机构：

[1] Univ of California, Electr Eng &, Comput Sci Dep, Berkeley, CA, USA

来源：

IEEE ASSP magazine | 1988年 / 5卷 / 04期

关键词：

Computer Architecture - Computer Systems; Digital--Real Time Operation - Computers; Microcomputer;

D O I：

10.1109/53.16926

中图分类号：

学科分类号：

摘要：

The architectural features of single-chip programmable digital signal processors (DSPs) are explored. The focus is on the most basic such feature, the integration of a hardware multiplier/accumulator into the data path, and a more subtle feature, the use of several (up to six) independent memory banks. These features are studied in terms of the performance benefit and the impact on the user. Representative DSPs from three manufacturers are used to illustrate the ideas to compare different solutions to the same problems.

引用

页码：4 / 19