Low power design using double edge triggered flip-flops

被引：64

作者：

Hossain, Razak ^{[1
]}

Wronski, Leszek D. ^{[1
]}

Albicki, Alexander ^{[1
]}

机构：

[1] Univ of Rochester, Rochester, United States

来源：

IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1994年 / 2卷 / 02期

关键词：

Computational complexity - Computer architecture - Computer simulation - Electric network synthesis - Energy dissipation - Transistors;

D O I：

10.1109/92.285754

中图分类号：

学科分类号：

摘要：

In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on, the effect of input sequences, in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.

引用

页码：261 / 264