An 8-b 300MS/s folding and interpolating ADC for embedded applications

被引:3
作者
陆焱
林俪
夏杰峰
叶凡
任俊彦
机构
[1] StateKeyLaboratoryofASIC&System
关键词
analog-to-digital convertor; low-power; low-voltage; embedded; folding and interpolating;
D O I
暂无
中图分类号
TN792 [];
学科分类号
080902 ;
摘要
<正>A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter(ADC) is proposed.Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm2 active area,the ADC is especially suitable for embedded applications.The system is optimized for a low-power purpose.Pipelining sampling switches help to cut down the extra power needed for complete settling.An averaging resistor array is placed between two folding stages for power-saving considerations.The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input.Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.
引用
收藏
页码:153 / 158
页数:6
相关论文
共 3 条
[1]  
An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25?mm2[J] . Cheng Chen,Junyan Ren.Analog Integrated Circuits and Signal Processing . 2006 (2)
[2]  
Spatial filtering in flash A/D converters .2 PAN H,ABIDI A A. IEEE Trans on Circuits and Systems . 2003
[3]  
7 bit 800 Msps 120 mW folding and interpolation ADC using a mixed-averaging scheme .2 Makigawa K,Ono K,OhkawaA T. IEEE Symposium on VLSI Circuits Digest of Technical Papers . 2006