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On determining sensitization criterion in an iterative gate sizing process. How-Rern Lin,Hwang Ting Ting. IEEE tran CAD on IC and Syst . 1999
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Technology mapping for low power.In: IEEE DAC. Yeh C,Chang Chin-Chao,Wang Jinn-Shyan. New York . 1999
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Sequential logic optimization for low power using input-disabling precomputation architectures. Monteiro J,Devadas S,Ghosh A. In: IEEE Tran CAD of IC and Syst . 1998
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Clock-gating and its application to low power design of sequential circuits.In: IEEE Custom Integrated Circuits Conference. Wu Q,Pedram M,Wu W. New York . 1997
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Signal coding for low power: fundamental limits and practical realizations. Ramprasad S,Shanbhag N R,Hajj I N. IEEE Transactions on Very Large Scale Integration Systems . 1999
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Symbolicsynthesisofclock gatinglogicforpoweroptimizationofcontrol ori entedsynchronousnetworks. BeniniL,MicheliGDe,MaciiE ,etal. EuropeanDesignandTestConference . 1997
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System levelpoweroptimizationofspecialpurposeapplications :thebeachsolution. BeniniL,MicheliGiovanniDe,MaciiE ,etal. ProcLowPowerElectronicsandDesign . 1997
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Stochasticmodelingofapower managedsystem :constructionandoptimization. QiuQ,WuQ,PedramM. ProcLowPowerElectronicsandDesign . 1999
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Softwarecontrolledpowermanagement. LuYung Hsiang,SimunicT,MicheliGiovanniDe. 7thHardware/SoftwareCodesign，(CODES’’ 99) . 1999
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Selectiveinstructioncompressionformemoryenergyreductioninem beddedsystems. BeniniL,GiovanniDeMicheli,MaciiA ,etal. ProcLowPowerElectronicsandDesign . 1999