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A 1. 75GHz 3V dual -modulus divide-by-128 129 prescaler in 0. 7 m CMOS. Craninckx J,Steyaert M. IEEE Journal of Solid State Circuits . 1996
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A 320MHz,1. 5mW@1. 35V CMOS PLL for microprocessor clock generation. Von Kaenel V,Aebischer D,Piguet C,et al. IEEE Journal of Solid State Circuits . 1996
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High-speed architecture for a programmable frequency divider and a dual -modulus prescaler. Larsson P. IEEE Journal of Solid State Circuits . 1996
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The design of a CMOS current -adjustable charge-pump circuit insensitive to power supply and temperature. Zhao Hui,Xu Donglin,Pan Sha,et al. The Chinese Journal . 2003
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CMOS high-speed dual -modulus frequency divider for RF frequency synthesis. Foroudi N,Kwasniewski T A. IEEE Journal of Solid State Circuits . 1995
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[10]
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