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Partial and dynamic reconfiguration of FPGAs:a top down design methodology for an automatic implementation. Berthelot F,Nouvel F,Houzed D. IEEE Computer Society Annual symposium on emerging VLSI Technologies and Architectures . 2006
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A constant array multiplier core generator with dynamic partial evaluation architec ure selection. Yang B,,Joshi N,Karri R. 13th International Symposium on Field Programmable Gate Ar- rays . 2005
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Performance analysis of fixed,recon- figurable,and custom architectures for the SCAN image and video en- cryption. Dolla A,Kachris C,Bourbakis N. Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines . 2003
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Neural network training with con- strained integer weights. Plagianakos V P,Vrahatis M N. Proceedings of the 1999 Congress on Evolutionary Computation . 1999
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Converting integer to floating point number. He J,,Li V,Han Y Q. Proceedings of the 2003 International Conference on Neural Networks and Signal Processing . 2003