一种面向系统芯片的FPGA协同验证方法

Prototyping the M68060 for concurrent verification. Kumar J. IEEE Design and Test of Computers . 1997

Matching-based methods for high-performance clock routing. Cong J. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 1993

Resynthesis and retiming for optimum partial scan. Chakradhar S T,Dey S. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 1999

Static scheduling of multidomain circuits for fast functional verification. Kudugi M,Tessier R. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 2002

Improving a nonenumerative method to estimate path delay fault coverage. Heragu K. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 1997

Prototyping the M68060 for concurrent verification. Kumar J. IEEE Design and Test of Computers . 1997

Matching-based methods for high-performance clock routing. Cong J. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 1993

Resynthesis and retiming for optimum partial scan. Chakradhar S T,Dey S. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 1999

Static scheduling of multidomain circuits for fast functional verification. Kudugi M,Tessier R. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 2002

Improving a nonenumerative method to estimate path delay fault coverage. Heragu K. IEEE Transcations on Computer Aided Design of Integrated Circuits and Systems . 1997