共 19 条
[1]
A 14-b 12-MS/s CMOS pipelineADC with over 100-dB SFDR. Chiu Y,Gray P R. IEEE J Sol StaCirc . 2004
[2]
A20GS/s8b ADC with a1MB memory in0.18μm CMOS. Poulton K,Neff R,Setterberg B,et al. IEEE International Solid-State Circuits Conference . 2003
[3]
A20GS/s8b ADC with a1MB memory in0.18μm CMOS. Poulton K,Neff R,Setterberg B,et al. IEEE International Solid-State Circuits Conference . 2003
[4]
A background cali-bration technique for multibit/stage pipelined and ti me-interleaved ADCs. EL-SANKARY K,SAWAN M. IEEE Trans Circ SystⅡ . 2006
[5]
A0.5V8-bit10MSPS pipelined ADCin90nm CMOS. SHEN J-H,KINGET P. Symp VLSI Circ . 2007
[6]
A10b25MS/s4.8mW0.13μm CMOS ADCfor digital multi media broadcasting applications. CHO YJ,SA D H,KI M Y W,et al. CICC . 2006
[7]
A28mW10b80MS/s pipelined ADC in0.13μm CMOS. BOGNER P. Int Symp Circ and Syst . 2004
[8]
A1V11b200MS/s pipelined ADC with digital background calibrationin65nm CMOS. HSUEH K-W,CHOU Y-K,TU Y-H,et al. Int Sol Sta Circ Conf . 2008
[9]
A 1-GS/s 11-bit ADC With 55-dB SNDR,250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture. S.K.Gupta,,M.A.Inerfield,J.Wang. IEEE Journal of Solid State Circuits . 2006
[10]
A 16-bit 65-MS/s 3.3V pipe-line ADC core in SiGe BiCMOS with 78-dB SNR and180-fs jitter. ZANCHI A,TSAY F. IEEE Journal of Solid State Circuits . 2005