共 8 条
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Using second-order power analysis to attackDPA resistant software. Thomas Messerges. CryptographicHardware and Embedded Systems-CHES 2000 . 2000
[2]
Securing the AES finalists against power analysisattacks. Messerges T. Fast Software Encryption:7th Inter-national Workshop . 2001
[3]
Securing encryption algorithms agai-nst DPA at the logic level:Next generation smart card techno-logy. Tiri K,Ingrid Verbauwhede. Cryptographic Hardwareand Embedded Systems-CHES 2003:5th International Work-shop . 2003
[4]
A logic level design methodology for a se-cureDPA resistant ASIC or FPGA implementation. Tiri K,Verbauwhede I. Proceedings of Design,Automation and Test in Europe Conference(DATE) . 2004
[5]
Design and validation strategies for obtaining as-surance in countermeasures to power analysis and related attacks. Paul Kocher. NIST Physical Security Testing Workshop . 2005
[6]
Private circuitsII:Keeping secrets in tamperable circuits. Yuval Isha,Manoj Prabhakaran,Amit Sahai,et al. Proceedings of EuroCrypt . 2006
[7]
Correlation poweranalysis with a leakage model. Eric Brier,Christophe Clavier,Francis Olivier. Cryptographic Hardware and Embedded Systems-CHES2004:6th International Workshop . 2004
[8]
Multi-channelattacks. Dakshi Agrawal,,Josyula R Rao,Pankaj Rohatgi. Cryptographic Hardwareand EmbeddedSystems-CHES 2003:5th International Work-shop . 2003