基于FPGA的实时双精度浮点矩阵乘法器设计

被引：21

作者：

田翔 ^{[1
]}

周凡 ^{[1
]}

陈耀武 ^{[1
]}

刘莉 ^{[2
]}

陈耀 ^{[2
]}

机构：

[1] 浙江大学数字技术及仪器研究所

[2] 通用电气中国研发中心

来源：

浙江大学学报(工学版) | 2008年 / 09期

关键词：

矩阵乘法; 现场可编程门阵列; 双精度浮点矩阵; 并行结构; 稀疏矩阵;

D O I：

暂无

中图分类号：

TP332.22 [];

学科分类号：

摘要：

设计了一个并行结构双精度浮点矩阵乘法器以提高矩阵乘法的计算性能,并在Xilinx Virtex-4 SX55现场可编程门阵列(FPGA)上完成了方案的实现.乘法器中的处理单元采用阵列结构,在单个FPGA芯片中可集成25个处理单元,峰值计算性能达到3000 MFLOPS.针对工程实际中大量存在的包含稀疏矩阵的乘法问题,增加了预处理模块以避免零元素块参与计算,从而缩短了计算时间.通过对不同维数的稠密矩阵乘法以及稀疏矩阵乘法实验结果的分析,证实了本设计达到了较高的计算性能.

引用

页码：1611 / 1615

页数：5

共 10 条

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