共 12 条
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Impacts of loop optimization on power consumption ?? a fresh look. Yang Hong-bo,Gao, G.R.,Marquez, A., et al. Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP) . 2001
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EARTH: An efficient architecture for running threads[Ph D dissertation]. K B Theobald. . 1999
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Supportingfine-grained synchronization on a simultaneous multithreadingprocessor. DeanM Tullsen,,JackL L o,SusanJEggers etal. Proc of the5 thInt’’ lSymponHighPerform anceCom puterArchitecture . 1999
[4]
A compilation framework forpower and energy management on mobile computers. U Kremer,J Hicks,J Rehg. The14 thInt’’ lWorkshop onParallelComputing(LCPC’’01) . 2001
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Power-sensitivemultithreaded architecture. J S Seng,D M Tullsen,G Z N Cai. Proc oftheInt’’ lConf onComputerDesign2000 . 2000
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ILP versus TLP on SMT. Nicholas,Larry Carter,Jeanne Ferrante,Dean Tullsen. Supercomputing ‘99 . 1999
[7]
Compiler-Directed dynamic voltage/frequency scheduling for energy reduction in microprocessors. Hsu C-H.,Kremer U.,Hsiao M. International Symposium on Low Power Electronics and Design (ISLPED’01) . 2001
[8]
Simultaneous Multithreading: A Platform for Next-generation Processors. Eggers Susan,Emer Joel,Levy Henry, et al. IEEE Micro Magazine . 1997
[9]
Simultaneous multithreading: Maximizing on-chip parallelism. D M Tullsen,S J Eggers,H M Levy. In: 25 Years of the Int’ l Symp on Computer Architecture: Selected Papers . 1998
[10]
Reduceing power with dynamic critical path information. Seng, J.S,Tune, E.S,Tullsen, D.M. Proceedings of the 34th Annual International Symposium on Microarchitecture . 2001