高速浮点运算单元的FPGA实现

[1] Analysis of high-per-formance floating-point arithmetic on FPGAs. GOVINDUG,ZHUO L,CHOI S,et al. Proceed-ings of the 18th International Parallel and Distributed Process-ing Symposium . 2004

[2] Design of a field-programmable du-al-precision floating-point arithmetic unit. DINIZ P C,GOVINDUG. Proceedings of16th International Conference on Field Programmable Logicand Applications . 2006

[3] Open source high per-formance floating-point modules. HEMMERTK S,UNDERWOOD K D. Proceedings of the 14thAnnual IEEE Symposium on Field-Programmable CustomComputing Machines . 2006

[4] An IEEE compliantfloating-point adder with the deeply pipelining paradigm onFPGAs. SHAO Jie,YE Ning,ZHANG Xiaoyan. Proceedings of 2008 International Conference onComputer Science and Software Engineering . 2008

[5] Effective implementation of float-ing-point adder using pipelined LOP in FPGAS. MALIK A,KO Seok-Bum. Proceed-ings of Canadian Coufereuce on Electrical and Computer Engi-neering . 2005

[6] Novel and efficient 4∶2 and 5∶2 compressors with minimumnumber of transistors designed for low-power operations. GOPINEEDI P D,THAPLIYAL H,SRINIVAS M B,et al. Proceedings of the 2006 International Conference on Embed-ded Systems and Applications . 2006

[7] Leading-one prediction with con-current position correction. Bruguera,J,Lang,T. IEEE Transactions on Computers . 1999

[8] Design of verydeep pipelined multipliers for FPGAs. PANATO A,SILVA S,WAGNER F,et al. Proceedings ofDesign,Automation and Test in Europe Conference and Exhi-bition . 2004

[1] Analysis of high-per-formance floating-point arithmetic on FPGAs. GOVINDUG,ZHUO L,CHOI S,et al. Proceed-ings of the 18th International Parallel and Distributed Process-ing Symposium . 2004

[2] Design of a field-programmable du-al-precision floating-point arithmetic unit. DINIZ P C,GOVINDUG. Proceedings of16th International Conference on Field Programmable Logicand Applications . 2006

[3] Open source high per-formance floating-point modules. HEMMERTK S,UNDERWOOD K D. Proceedings of the 14thAnnual IEEE Symposium on Field-Programmable CustomComputing Machines . 2006

[4] An IEEE compliantfloating-point adder with the deeply pipelining paradigm onFPGAs. SHAO Jie,YE Ning,ZHANG Xiaoyan. Proceedings of 2008 International Conference onComputer Science and Software Engineering . 2008

[5] Effective implementation of float-ing-point adder using pipelined LOP in FPGAS. MALIK A,KO Seok-Bum. Proceed-ings of Canadian Coufereuce on Electrical and Computer Engi-neering . 2005

[6] Novel and efficient 4∶2 and 5∶2 compressors with minimumnumber of transistors designed for low-power operations. GOPINEEDI P D,THAPLIYAL H,SRINIVAS M B,et al. Proceedings of the 2006 International Conference on Embed-ded Systems and Applications . 2006

[7] Leading-one prediction with con-current position correction. Bruguera,J,Lang,T. IEEE Transactions on Computers . 1999

[8] Design of verydeep pipelined multipliers for FPGAs. PANATO A,SILVA S,WAGNER F,et al. Proceedings ofDesign,Automation and Test in Europe Conference and Exhi-bition . 2004