基于FPGA的字串行FIR滤波器的实现

Low_latency bit_parallel Systolic VLSI Implementation of FIR Digital Filters. Caraiscos C G,Pekmestzi K Z. IEEE Circuits and Systems Magazine . 1996

A Systematic Approach for Design of Digit_serial Signal Processing Architectures. Parhi K K. IEEE Circuits and Systems Magazine . 1991

Performance Evaluation and Optimal design for FPGA_based Digit_serial DSP Functions. Hanho Lee,Sobelman G E. Computers and Electrical Engineering . 2003

Bit_level Pipelined Digit_serial Array Processors. Aggoun A,Ibrahim M K,Ashur A. IEEE Circuits and Systems Magazine . 1998

Low_latency bit_parallel Systolic VLSI Implementation of FIR Digital Filters. Caraiscos C G,Pekmestzi K Z. IEEE Circuits and Systems Magazine . 1996

A Systematic Approach for Design of Digit_serial Signal Processing Architectures. Parhi K K. IEEE Circuits and Systems Magazine . 1991

Performance Evaluation and Optimal design for FPGA_based Digit_serial DSP Functions. Hanho Lee,Sobelman G E. Computers and Electrical Engineering . 2003

Bit_level Pipelined Digit_serial Array Processors. Aggoun A,Ibrahim M K,Ashur A. IEEE Circuits and Systems Magazine . 1998