共 10 条
[1]
Performance of PLL synthesizer based on DDS feedback. Brennan PV. Electronics Letters . 1998
[2]
“A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation,”. A. Sodagar,and G. Lahiji. IEEE Transactions on Circuits and Systems . 2001
[3]
Low-power direct digitalfrequency synthesis for wireless communications. Bellaouar A,O’brecht M S,Fahim A M. IEEE Journal of Solid State Circuits . 2000
[4]
An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation. Nicholas III H T and Samueli H. 41st Annual Frequency Control Symp . 1987
[5]
A 150-MHz direct digital frequency synthesizer in 1. 25-μm CMOS with -90dBc spurious performance. Henry T Nicholas,III Henry Samueli. IEEE Journal of Solid State Circuits . 1991
[6]
A Novel DDS Using Nonlinear ROM Ad-dressing With Improved Compression Ratio and QuantizationNoise. Lakshmi S.Jyothi Chimakurthy,Malinky Ghosh,Foster DaiFa,Jaeger Richard C. IEEE Transactions on Ultrasonics Ferroelectricsand Frequency Control . 2006
[7]
Phase to Sinusoid Amplitude Conversion Techniques for Direct Digital Frequency Synthesis. J. M. P. Langlois and D. Al-Khalili. IEE Proceedings-Circuits,Devices and Systems . 2004
[8]
A High Resolution Phase and Frequency OffsetGenerator. Ascarrunz F G. IEEE International Frequency Control Sympo-sium . 1998
[9]
Direct Digital Synthesizer WithSine-Weighted DAC at 32 GHz Clock Frequency in InP DH-BT Technology. Turner S E,Kotechi D E. IEEE Journal of Solid State Circuits . 2006
[10]
A Digital Frequency Synthesizer. J. Tierney,C.M. Rader and B. Gold. IEEE Transactions on Audio and Electroacoustics . 1971