时间交替ADC系统的一种动态误差补偿方法

被引:4
作者
张昊
师奕兵
王志刚
机构
[1] 电子科技大学自动化工程学院
关键词
时间交替ADC系统; 模数转换器; 无杂散动态范围; 动态误差;
D O I
10.19650/j.cnki.cjsi.2009.11.008
中图分类号
TN792 [];
学科分类号
080902 ;
摘要
目前有许多方法被用于补偿或减少时间交替ADC系统各个通道失配带来的误差,但这类方法仅考虑了静态效果,没有提供一种测量时间交替ADC系统误差的有效方法,对SFDR提高非常有限,并且难以满足实时性的要求。本文采用由状态空间索引的误差表对时间交替ADC系统的输出进行校准。该方法将某一通道作为参考通道,对其它通道的误差进行测量并生成由时间交替ADC系统输出状态索引的误差表,利用该误差表对各个通道的输出进行动态校准。最后将该方法用于400 MSPS/12 bit高速数字化仪的校准,在输入幅度为1V的1MHz正弦信号时,高速数字化仪的杂散失真可降低20 dB。
引用
收藏
页码:2279 / 2284
页数:6
相关论文
共 10 条
[1]  
The impact of combined channel mismatch effects in time-interleaved ADCs. Vogel C. IEEE Transactions on Instrumentation and Measurement . 2005
[2]  
Analysis of mismatcheffects among A/Dconverters in atime-interleaved waveformdigitizer. S K Mitra,APetraglia. IEEE Transactions on Instrumentation and Measurement . 1991
[3]  
An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters. Dyer K C,Fu D H,Lewis S H. IEEE Journal of Solid State Circuits . 1998
[4]  
A Digital Background Calibration Technique for Ti me-Interleaved Analog-to-Digital Converters. Fu Daihong,Dyer Kenneth C,Lewis Stephen H,and Hurst Paul J. IEEE Journal of Solid State Circuits . 1998
[5]  
A 10-bit 120-Msample/s time-interleaved analog-to-digital converter withdigital background calibration. Jamal S M,Daihong Fu,Chang N C J, et al. IEEE Journal of Solid State Circuits . 2002
[6]  
A20GS/s8b ADC with a1MB memory in0.18μm CMOS. POULTON K,,NEFF R,SETTERBERG B,et al. Proc.IEEE Int.Solid-State Circuits Conf . 2003
[7]  
Time-interleaved oversampling A/D converters:theory and practice. KHOINI-POORFARD R,LIM L.B,,JOHNS D A. IEEE trans.Circuits syst.II . 1997
[8]  
A4GSample/s8b ADC in0.35μm CMOS. POULTON K,NEFF R,MUTO A,et al. Int.Solid-State Circuits Conf.Tech.Dig . 2002
[9]  
Digital offset compensa-tion of time-interleaved ADC using random chopper sam-pling. EKLUND J.E,,GUSTAFSSON F. Proc.IEEE Int.Symp.Circuits syst.ISCAS . 2000
[10]  
Time-interleaved oversampling converters. Poorfard,R.K.,Johns,D.A. Electronics Letters . 1993