Electrical behavior of decoupling capacitors embedded in multilayered PCBs

In this paper, we describe the modeling of prototype capacitors embedded in multilayered printed circuit boards. We present the design of these devices. We also report measurement and characterization results. The emphasize is on the modeling of via hole connections to the embedded capacitor, not on the technology of buried capacitors in se. Several designs have been compared with respect to their electrical behavior. In particular, several via hole configurations have been studied, because they are the main cause of parasitic behavior. With these buried capacitors, we obtained a reduction of the parasitic inductance of 80% compared to an equivalent discrete capacitor. This work has been carried out under a European Brite-EuRAM funded project COMPRISE (BE 96-3371). The objective of this project was to develop new materials and manufacture processes to embed passive components (R, L, and C) within printed wiring structures fabricated from laminate materials. This technology enables the manufacture of space efficient and radio frequency (RF) optimal performing types of modules or board assemblies particularly suited to the market domain of portable and handheld communication and information technology products.