Statistically based prediction of power dissipation for complex embedded DSP processors

This paper presents an empirical methodology for low power driven design of complex DSP embedded systems. Unlike previous techniques, the methodology derives power prediction models from software derived parameters, uses statistical optimization, and verifies results with real power measurements. The methodology is general and is applied to two widely different DSP processors (a single multiplier-accumulator, highly heterogeneous architecture and the other a VLIW-based architecture with eight functional units). Based on over 180 power measurements of DSP code, derived models are shown to predict power with less than 4% error. Results show that variables derived directly from the DSP assembly code can be used to produce highly accurate power models. This result is important for developing a general methodology for power characterization of embedded DSP software since low power is critical to complex DSP applications in many cost sensitive markets. (C) 1999 Elsevier Science B.V. All rights reserved.