D0 muon readout electronics design

被引:3
作者
Baldin, B
Bardon, O
Fitzpatrick, T
Golovtsov, V
Hansen, S
Larwill, M
Los, S
Matveev, M
Neustroev, P
Podstavkov, V
Rotolo, C
Uvarov, L
Vaniev, V
Wood, D
机构
[1] IHEP,PROTVINO 142284,MOSCOW REGION,RUSSIA
[2] NORTHEASTERN UNIV,BOSTON,MA 02115
[3] PNPI,ST PETERSBURG 188350,GATCHINA,RUSSIA
关键词
D O I
10.1109/23.603672
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The readout electronics designed for the DO Muon Upgrade [1] are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the DO Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16-bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed.
引用
收藏
页码:363 / 369
页数:7
相关论文
共 4 条
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1995, 42 (04) :736-742
[2]  
*DO COLL, 1996, FERMILABPUB96357E DO
[3]  
JAYANTI R, 1996, 2780 DO FERM
[4]  
WIGHTMAN JA, 1996, COMMUNICATION 1022