Effect of chip and bonding defects on the junction temperatures of high-brightness light-emitting diodes

Light-emitting diodes (LEDs) are a strong candidate for the next-generation general illumination applications. LEDs are making great strides in brightness performance and reliability; however, the barrier to widespread use in general illumination still remains the cost (dollars per lumen). LED packaging designers are pushing the LED performance to its limits. This is resulting in increased drive currents and thus the need for lower-thermal-resistance packaging. The efficiency and reliability of solid-state lighting devices strongly depends on successful thermal management, because the junction temperature of the chip is the prime driver for effective operation. As the power density continues to increase, the integrity of the package electrical and thermal interconnects becomes extremely important. Experimental results with high-brightness LED packages show that chip attachment defects can cause significant thermal gradients across the LED chips, leading to premature failures. Perfect chip and interconnect structures for highly conductive substrates showed only a 2 K temperature variation over a chip area of approximately 1 mm(2), while defective chips experienced greater than 40 K temperature variations over an identical area. A further numerical study was also carried out with parametric finite-element models to understand the temperature profile variation of the chip active layer due to the bump defects. Finite-element models were utilized to evaluate the effects of hot spots in the chip active layer. The importance of zero defects in one of the more popular interconnect schemes - the epi-down soldered flip-chip configuration - is investigated and demonstrated. (c) 2005 Society of Photo-Optical Instrumentation Engineers.