DC-link capacitors voltage balancing in multilevel four-leg diode-clamped converters

被引：22

作者：

León, JI ^{[1
]}

Franquelo, LG ^{[1
]}

Portillo, R ^{[1
]}

Prats, MM ^{[1
]}

机构：

[1] Univ Seville, Dept Elect Engn, Seville 41092, Spain

来源：

IECON 2005: THIRTY-FIRST ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-3 | 2005年

关键词：

D O I：

10.1109/IECON.2005.1569085

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Multilevel four-leg four-wire converters are creating increasing interest nowadays in applications as active filters. They present several advantages compared to the three-leg converter topologies. Recently the control complexity has been reduced thanks to the use of new and powerful microprocessor systems, hence the balance of the DC-link voltage is the major drawback of this kind of topologies. In this paper, the first control strategy to carry out the balance of the DC-link voltage in the multilevel four-leg four-wire Diode-Clamped Converter is presented. This strategy uses the known technique based on choosing the most suitable redundant vector in the Space Vector Modulation algorithm in order to reduce the unbalance. It is important to notice that the proposed method is independent of the load and independent of the number of levels of the converter. Some simulation results show the obtained balance using the proposed technique.

引用

页码：1254 / 1259

页数：6

共 6 条

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Franquelo, L. G. ;

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Portillo, R. ;

Leon, J. I. ;

Perales, M. ;

Carrasco, J. M. ;

Galvan, E. ;

Mora, J. L. .

IECON 2004: 30TH ANNUAL CONFERENCE OF IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOL 3, 2004, :2285-2289

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