A novel resistance memory with high scalability and nanosecond switching

被引：163

作者：

Aratani, K. ^{[1
]}

Ohba, K. ^{[1
]}

Mizuguchi, T. ^{[1
]}

Yasuda, S. ^{[1
]}

Shiimoto, T. ^{[1
]}

Tsushima, T. ^{[1
]}

Sone, T. ^{[1
]}

Endo, K. ^{[1
]}

Kouchiyama, A. ^{[1
]}

Sasaki, S. ^{[1
]}

Maesaka, A. ^{[1
]}

Yamada, N. ^{[1
]}

Narisawa, H. ^{[1
]}

机构：

[1] Sony Corp, Informat Technol Labs, Solid State Memories Res Lab, Kanagawa 2430021, Japan

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4419064

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We report a novel nonvolatile dual-layered electrolytic resistance memory composed of a conductive Cu ion activated layer and a thin insulator for the first time. An ON/OFF mechanism of this new type memory is postulated as follows: Cu ions pierce through the insulator layer by applied electric field, the ions form a Cu conductive bridge in the insulator layer, and this bridge dissolves back to the ion activated layer when the field is reversed. The 4 kbit memory array with 1T-1R cell structure was fabricated based on 180 nm CMOS process. Set/reset pulses were 5 ns, 110 mu A and 1 ns, 125 gA, respectively Those conditions provide large set/reset resistance ratio of over 2 orders of magnitude and satisfactory retention. Essential characteristics for high capacity memories including superb scalability down to 20 nm phi, sufficient endurance up to 10(7) cycles and preliminary data for 4-level memory are also presented. These characteristics promise the memory being the next generation high capacity nonvolatile memory even before the scaling limitation of flash memories is encountered.

引用

页码：783 / 786

页数：4

共 5 条

[1]

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[2]

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Kozicki, MN ;

Gopalan, C ;

Balakrishnan, M ;

Park, M ;

Mitkova, M .

2004 NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM, PROCEEDINGS, 2004, :10-17

[4]

LEE KJ, 2007, IEEE INT SOL STAT CI, P472, DOI DOI 10.1109/ISSCC.2007.373499

[5]

MANTEGAZZA D, 2006, IEDM, P53

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