MicroSMD - A wafer level chip scale package

被引：20

作者：

Kelkar, N ^{[1
]}

Mathew, R ^{[1
]}

Takiar, H ^{[1
]}

Nguyen, L ^{[1
]}

机构：

[1] Natl Semicond Corp, Santa Clara, CA 95052 USA

来源：

IEEE TRANSACTIONS ON ADVANCED PACKAGING | 2000年 / 23卷 / 02期

关键词：

chip scale package; CSP assembly; CSP rework; package reliability; wafer level packaging;

D O I：

10.1109/6040.846639

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD, This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.

引用

页码：227 / 232

页数：6