PN and SOI wafer flow process for stencil mask fabrication

被引：8

作者：

Butschke, J ^{[1
]}

Ehrmann, A ^{[1
]}

Haugeneder, E ^{[1
]}

Irmscher, M ^{[1
]}

Käsmaier, R ^{[1
]}

Kragler, K ^{[1
]}

Letzkus, F ^{[1
]}

Löschner, H ^{[1
]}

Mathuni, J ^{[1
]}

Rangelow, IW ^{[1
]}

Reuter, C ^{[1
]}

Shi, F ^{[1
]}

Springer, R ^{[1
]}

机构：

[1] Inst Mikroelekt Stuttgart, D-70569 Stuttgart, Germany

来源：

15TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS '98 | 1999年 / 3665卷

关键词：

D O I：

10.1117/12.346224

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two process flows for the fabrication of stencil masks have been developed. The PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6" Si base wafers with 3 mu m membrane thickness and a membrane diameter between 120mm and 126mm were fabricated. The membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.

引用

页码：20 / 29

页数：10

共 7 条

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