Interface finite-state machines: Definition, minimization, and decomposition

被引:1
作者
Daga, AJ [1 ]
Birmingham, WP [1 ]
机构
[1] UNIV MICHIGAN, DEPT ELECT ENGN & COMP SCI, ANN ARBOR, MI 48109 USA
基金
美国国家科学基金会;
关键词
D O I
10.1109/43.631212
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
There is a well-recognized need for accurate timing verification tools that account for the functional behavior of component interfaces, and thereby do not traverse false combinational and sequential paths. Such tools, however, are susceptible to an exponential increase in task complexity as the circuit size and functional complexity of components increase. The viability of accurate timing verifiers hinges on their ability to efficiently analyze the smallest subset of circuit behaviors, while verifying the timing characteristics of the overall space of behaviors. This paper presents theoretical results that address this issue for the timing verification of interacting FSM's.
引用
收藏
页码:497 / 505
页数:9
相关论文
共 11 条
[1]  
DAGA AJ, 1995, THESIS U MICHIGAN AN
[2]  
DAGA AJ, 1995, P IEEE INT C COMP DE
[3]   COMPUTATION OF FLOATING MODE DELAY IN COMBINATIONAL-CIRCUITS - THEORY AND ALGORITHMS [J].
DEVADAS, S ;
KEUTZER, K ;
MALIK, S .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (12) :1913-1923
[4]  
DU DHC, 1989, P 26 IEEE ACM SIGDA
[5]  
GUPTA A, 1994, P 31 IEEE ACM DES AU
[6]  
HITCHCOCK RB, 1982, P 19 IEEE ACM SIGDA
[7]  
Kohavi Z., 1978, Switching and Finite Automata Theory, V2nd
[8]  
McGeer P.C., 1991, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
[9]  
MCGEER PC, 1991, P IEEE INT C COMP AI
[10]  
RIEPE MA, 1994, P INT C COMP AID DES