Mismatch characterization of submicron MOS transistors

The characterization of transistor mismatch in a standard 0.7 mu m CMOS technology is presented. A new method for matching parameter extraction has been used. Mismatch parameters based on measurements on 10000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 0.7 mu m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed. Contrary to the established theory, it is observed that transistors with channel length below 1 mu m have less current mismatch than what is predicted by a linear relationship with the channel area.