Commercially available photoresists for 193nm litho technology still suffer of undesired phenomena, which could eventually limit the stability of critical layer processing. Also standard CD-SEM inspection has its impact on the overall litho budget, as the interaction between the primary electron beam and the photoresist locally modifies target dimension. The reduction of this effect can be important to preserve geometrical and also electrical characteristics of the chip, as the local variation of the CD is detectable also after target etching and resist removal. In this paper different strategies to reduce its impact onto production wafers are investigated and compared. By applying a combination of these techniques, CD local modification can be lowered up to 75%.