A 3-D stacked chip packaging solution for miniaturized massively parallel processing

被引:20
作者
Lea, RM [1 ]
Jalowiecki, IP
Boughton, DK
Yamaguchi, JS
Pepe, AA
Ozguz, VH
Carson, JC
机构
[1] Brunel Univ, Uxbridge UB8 3PH, Middx, England
[2] Aspex Microsyst Ltd, Uxbridge UB8 3PH, Middx, England
[3] Irvine Sensors Corp, Costa Mesa, CA 92626 USA
来源
IEEE TRANSACTIONS ON ADVANCED PACKAGING | 1999年 / 22卷 / 03期
关键词
associative processing; defect/fault tolerance; high density interconnect; massively parallel processor implementation; three-dimensional (3-D) chip stacking;
D O I
10.1109/6040.784496
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The development and evaluation of a three-dimensional (3-D) interconnect and packaging technology for massively parallel processor (MPP) implementation is reported. Following reviews of specific modular massively parallel computer (MPC) accelerator and chip stacking technologies, the paper reports the progress of a collaborative research project to pioneer a novel MPP module. The design of a highly compact 3-D chip-stack, integrating five MPP chips in a single package, is described in detail. Problems encountered and their solutions are reported. Test results for prototype MPP chip-stacks provide proof-of-principle for the 3-D chip stacking approach. Allowing from 2:1 to 4:1 savings in the modular MPC implementation size, without significant increase in cost or loss of performance, the emerging MPP chip stacking technology offers a cost-effective solution for MPP miniaturization.
引用
收藏
页码:424 / 432
页数:9
相关论文
共 11 条
  • [1] CAMPBELL ML, 1993, P INT C WAF SCAL INT, P67
  • [2] CARSON J, 1996, P INT C INN SYST SIL, P1
  • [3] A modular massively parallel computing approach to image-related processing
    Krikelis, A
    Lea, RM
    [J]. PROCEEDINGS OF THE IEEE, 1996, 84 (07) : 988 - 1004
  • [4] KURINO H, 1997, P INT C INN SYST SIL, P203
  • [5] ASSOCIATIVE MASSIVELY PARALLEL COMPUTERS
    LEA, RM
    JALOWIECKI, IP
    [J]. PROCEEDINGS OF THE IEEE, 1991, 79 (04) : 469 - 478
  • [6] ASP - A COST-EFFECTIVE PARALLEL MICROCOMPUTER
    LEA, RM
    [J]. IEEE MICRO, 1988, 8 (05) : 10 - 29
  • [7] WAFER-SCALE INTEGRATION OF SYSTOLIC ARRAYS.
    Leighton, Tom
    Leiserson, Charles E.
    [J]. IEEE Transactions on Computers, 1985, C-34 (05) : 448 - 461
  • [8] MINAHAN JA, 1992, P ELECTR C, P340
  • [9] A DEVICE LIFE-CYCLE ANALYSIS OF THE WSI ASSOCIATIVE STRING PROCESSOR
    PEACOCK, C
    BOLOURI, H
    LEA, RM
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1995, 18 (03): : 406 - 415
  • [10] Sheridan N. G., 1992, Proceedings. International Conference on Wafer Scale Integration (Cat. No.92CH3088-2), P115, DOI 10.1109/ICWSI.1992.171802